1. Field of the Invention
The present invention relates to a semiconductor fabrication method. More particularly, the present invention relates to a method of fabricating a bottom electrode.
2. Description of the Related Art
As the integration of the semiconductor devices increases and the linewidth thereof decreases, it becomes desirable to form more semiconductor devices in a very limited area. Due to limitations imposed by the fabrication process, it is difficult to achieve a highly integrated circuit. In addition, because difficulties exist in forming a highly integrated device, it is hard to ensure the reliability of the device. Therefore, how to fabricate highly integrated semiconductor devices has became the main topic of the recent research on semiconductor fabrication at the 0.13 micron level.
FIG. 1 is a schematic, cross-sectional view illustrating a conventional method of forming a bit line and a bottom electrode.
A metal oxide semiconductor (MOS) is formed on the substrate 100. The MOS includes a gate 102 on the substrate 100, a spacer 104 on the sidewall of the gate 102 and the source/drain region 106 in the substrate 100 beside the gate 102. A dielectric layer 108 is formed over the substrate 100 to cover the MOS. A bit line 110 is formed through the dielectric layer 108 to electrically couple with the source/drain region 106. A dielectric layer 112 is formed over the substrate 100 to cover the bit line 110. A bottom electrode 114 is formed through the dielectric layers 108 and 112 to electrically couple with the source/drain region 106.
In the conventional method, devices, such as bit line 110 and the bottom electrode 114 are separated from each other. Consequently, the integration of the semiconductor circuit cannot be effectively increased. Thus, there is a need to further increase the integration of semiconductor devices.
In addition, due to the fabrication limitation for forming semiconductor devices in a limited area, box-shaped capacitors are usually formed. However, the conventional box-shaped capacitor cannot provide sufficient capacitance. Thus, the capacitance of the conventional capacitor is limited.
The invention provides a method of fabricating a bottom electrode. A substrate having a conductive layer therein is provided. A first dielectric layer is formed over the substrate. A conductive plug is formed through the first dielectric layer to electrically couple with the conductive layer. A cap layer is formed over the substrate to cover the conductive plug. An isolation layer is formed over the cap layer. A plurality of bit lines is formed over the isolation layer. A second dielectric layer is formed over the isolation layer. A node contact opening is formed through the second dielectric layer, the bit lines and the isolation layer to expose the cap layer. A conformal isolation layer is formed over the substrate to partially fill the contact node opening. A third dielectric layer having an opening is formed over the substrate. The opening is aligned with the node contact opening. An etching step is performed to remove a portion of the conformal isolation layer exposed by the opening and the cap layer. An isolation spacer remaining from the conformal isolation layer is formed on a sidewall of the contact node opening. A conformal conductive layer is formed in the opening and the node contact opening to make contact with the conductive plug. The third dielectric layer is removed.
In contrast with the conventional method, which has the bit line and the bottom electrode far way from each other, the bit lines and the bottom electrode of the present invention are next to each other. Thus, the integration of the semiconductor devices fabricated by the present invention is effectively increased. In addition, since the isolation spacer is used to isolate the bit lines from the bottom electrode, the reliability of the devices is enhanced. Furthermore, in comparison with the box-shaped bottom electrode formed by the conventional method, the bottom electrode of the present invention has an increased surface area.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.